It is often possible to increase the performance of an electronic system by increasing the utilization of a bus in the system. For example, it might be possible to increase the performance of a computer system having a Peripheral Component Interconnect (PCI) bus according to the PCI Local Bus Specification, Revision 2.1, published July 1995, by increasing the utilization of the PCI bus.
According to a well known approach, wait states are inserted into a pending PCI transaction when the device that is the target of the transaction is not ready to complete the transaction. Wait states continue to be inserted until either the target is ready to complete the transaction or a timer in the target expires. In either case, the bus is not available for other transactions during the pending transaction. If another bus master is ready to initiate another transaction during the pending transaction, then a potential increase in bus utilization will be lost. Also, in the case of termination due to an expiring timer, a potential increase in bus utilization will be lost if the target would have been ready to complete the transaction after the timer expires but before another bus master is ready to initiate a transaction.
Therefore, a novel approach to terminating a bus transaction if the target is not ready has been developed.